1. Technical Field
The present disclosure relates to a memory controller. Particularly, embodiments of the present disclosure relate to a memory controller capable of changing values of timing parameters in consideration of a time lapsed after a refresh operation is completed.
2. Related Art
In general, a DRAM device includes a plurality of banks. When requests from an external device, e.g., host, are properly distributed to the plurality of banks, the occurrence probability of a bottleneck phenomenon is reduced. However, a bottleneck phenomenon may occur when a plurality of requests are concentrated on one bank as a result of trying to sequentially process these requests.
When the plurality of requests are related to the same row address, the occurrence probability of the bottleneck phenomenon is relatively reduced since a row access operation is performed only once, while a column access operation is performed several times.
However, it may not be possible to avoid delay of processing time when the plurality of requests are related to row addresses that are different from one another since a separate row access operation is performed for each request.
FIG. 1 is an exemplary timing graph related to a row access operation of a DRAM device. The timing graph illustrated shows multiple row access operations (indicated as “row cycle time”) that may be performed serially over time.
As further illustrated in FIG. 1, a particular row access operation, which may require a certain amount (e.g., “row cycle time” in FIG. 1) of time to complete, may actually involve multiple operations related to precharge, charge sharing, amplification, and recovery stages, wherein when each row access operation is performed timing parameters such as tRP (row precharge time), tRCD (row address to column address delay), IRAS (row active time), and tRC (row cycle time) should be satisfied as illustrated in FIG. 1.
Since a conventional memory controller applies constant timing parameters to multiple row access operations, when the multiple row access operations are performed as illustrated in FIG. 1, it is difficult to avoid a bottleneck phenomenon. As a result, operational performance of a DRAM device is deteriorated.